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Design FlowMICROWIND supports entire front-end to back-end design flow.

For front-end designing, we have DSCH (digital schematic editor) which posses in-built pattern based simulator for digital circuits. User can also build analog circuits and convert them into SPICE files and use 3rd party simulators like WinSpice or pSPICE.

DSCH can convert the digital circuits into Verilog file which can be further synthesized for FPGA/CPLD devices of any vendor. The same Verilog file can be compiled for layout conversion in MICROWIND.

The back-end design of circuits is supported by MICROWIND. User can design digital circuits and compile here using Verilog file. MICROWIND automatically generates a error free CMOS layout. Although this place-route is not optimized enough as we do not indulge in complex place & route algorithms.

User can also create CMOS layout of their own using compile one line Verilog syntax or custom build the layouts by manual drawing.

The CMOS layouts can be verified using inbuilt mix-signal simulator and analyzed further for DRC, crosstalks, delays, 2D cross section, 3D veiw, etc.

For any queries, please contact us.


Click here to evaluate the lite version of Microwind