The adoption of nano-sheet FET should follow the adoption of FinFET with a 10-years shift. Is it anticipated that the 3-nm node will enable further gains in current drive while reducing the device surface, thus enabling smaller, faster and more energy-efficient chips. The three different categories of applications should remain: high performance computing (severs, data centers), general purpose (laptops, gaming), and low power (mobile, IoT) with significant differences in terms of acceptable leakage current (IOFF).
No n-well layer is required anymore as the device channel is totally surrounded by the gate, without any influence of the substrate as for MosFET & FinFET. Therefore, no polarization is required too, which enables to place n & p devices much closer to each other than previous technologies.
a stack of horizontal sheets of silicon.
The gate completely surrounds each sheet.
There is no n-well and no polarization is required.
The intra-cell interconnects are shorter
and lead to a capacitance & resistance reduction
The full control of the 4 sides of the
channel gives better Ion/Ioff performances than FinFET or MosFET.
Given a 1mA ION current, nano-sheet FET require 50% less silicon as compared to FinFET.
nsFET add a degree of freedom to circuit design that FinFETs lack.
In Microwind 3.9 you can generate nsFET transistors or compiler using Verilog file too. The mosfet layout generator of Microwind 3.9 will allow user to generate nsFET of their desired size.
Option to set gate length. thickness
nsFET comme with dummy gates for manufacturability
HD: High density drawing style
HP : High performance drawing style
The p-well layer in 3nm technology will be deactivated.